Key Responsibilities:

- Perform full-chip/block-level physical design including floorplanning, placement, CTS, routing, and optimization
- Drive timing closure with strong focus on Static Timing Analysis (STA)
- Handle signoff activities including:
- STA (Setup/Hold closure)
- Physical Verification (DRC/LVS)
- IR Drop and EM analysis

- Work on logic synthesis and ensure timing/power/area targets are met
- Perform and analyze VCLP (Voltage-aware checks) and LEC (Logical Equivalence Check)
- Collaborate with RTL, DFT, and backend teams for design convergence
- Debug and resolve timing, congestion, and power issues
- Implement and verify low power intent using UPF

Mandatory Skills:

- Strong hands-on experience in PNR (Place & Route) MUST
- Good expertise in Static Timing Analysis (STA) HIGH PRIORITY
- Experience in Synthesis and Signoff flows (STA, PV, IR/EM)
- Knowledge of VCLP / LEC flows
- Exposure to low power design techniques and UPF

Preferred Skills:

- Experience with industry-standard EDA tools (Cadence/Synopsys)
- Strong debugging and problem-solving skills
- Good understanding of semiconductor design flow
- Ability to work in a fast-paced, collaborative workplace

📌 Physical Design Engineer (Uttar Pradesh)
🏢 7rays Semiconductors
📍 Uttar Pradesh