Job Summary

We are seeking an experienced and highly motivated Senior Engineer to lead a team responsible for verification of high-speed PHY IPs. The ideal candidate combines deep technical expertise in digital design verification with strong leadership skills to drive execution, mentor engineers, and deliver high-quality verification solutions for next-generation PHY technologies.

This role requires close collaboration with Design, Architecture, AMS, Firmware, Physical Design, and Program Management teams to ensure first-pass silicon success.

Key Responsibilities

Technical Leadership

- Lead verification of complex high-speed PHY IPs such as DDR, LPDDR, PCIe, CXL, UCIe, Ethernet, USB, or SerDes.
- Own verification planning from architecture review through silicon bring-up support.
- Develop comprehensive verification strategies including:
- Test plans
- Functional coverage
- Assertion-based verification
- Constrained-random verification
- Formal verification where applicable

- Drive verification closure using coverage, bug convergence, and quality metrics.
- Review verification architecture, testbench design, and coding standards.
- Debug complex design and verification issues spanning digital, analog, and firmware interfaces.

Team Leadership

- Lead and mentor a team of verification engineers.
- Plan project execution, priorities, and resource allocation.
- Conduct technical reviews and provide constructive feedback.
- Drive engineering excellence through best practices, reusable methodologies, and automation.
- Foster a collaborative, learning-oriented engineering culture.
- Coach engineers on growth opportunities and technical development.

Cross-Functional Collaboration

- Partner closely with Design Engineers
- AMS Engineers
- Firmware Engineers
- Physical Design




- Architecture
- Emulation/Validation
- Program Management

to ensure alignment across all project phases.

Participate in architecture reviews to improve verification readiness early in the development cycle.

Methodology Development

Drive adoption and continuous improvement of

- UVM methodology
- SystemVerilog
- Assertion-based verification
- Regression infrastructure
- Coverage-driven verification
- CI/CD verification flows
- AI-assisted verification productivity
- Verification automation frameworks

Promote IP reuse and standardized verification environments across projects.

Project Execution

- Estimate verification effort and schedules.
- Track milestones and execution risks.
- Drive timely issue resolution.
- Report project status using measurable quality metrics.
- Support silicon validation and customer issue debugging when required.

Required Qualifications

- Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of ASIC/SoC verification experience.
- Experience leading technical teams or mentoring engineers.
- Strong expertise in:
- SystemVerilog
- UVM
- Assertions (SVA)
- Functional coverage
- Constrained-random verification

- Strong debugging skills.
- Experience with scripting languages such as Python, Perl, or Tcl.
- Experience with industry-standard simulators and regression environments.

Preferred Experience

Experience verifying one or more of:

- DDR5/LPDDR5/LPDDR6 PHY
- UCIe PHY
- PCIe Gen5/Gen6
- Ethernet PHY
- USB4
- Display PHY
- SerDes

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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