Product and Test Engineering with >10years experience on ATE (T2K, ETS364, 93K), HW design, TP development, debug, data analysis and presentation.

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- BSEE with minimum 1-5yrs of direct experience of Test & DFT Design knowledge
- Good programming skills using C/C++, Perl, Python
- Excellent communication and leadership skills, working with cross-functional teams across multiple different internal development and factory sites
- Excellent interpersonal skills energetic, motivated, and self-driven
- Demonstrate ability to work well within a global team environment with minimal supervision
- Outstanding written and verbal communication skills
- Robust organizational skills; demonstrate ability to manage multiple tasks

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ATE (T2K, ETS364, 93K), HW design, TP development, debug, data analysis and presentation.

1. Primary responsibilities:
1. Define product DFT and test requirements Pre-PG including: a) DfT-max Requirements for a new product b) translate PRD / MRDs into PTS / SCMs / PRPs for ATE test-plan definition c) design ATE HW for lowest cost solution (max multi-site, lowest pin-mux) for Si bring-up and validation
2. Post-Si bring-up and validation of all functional and test features. This includes extensive debug that will require good knowledge of IC design and semiconductor physics, with ability to clearly isolate and root-cause issues to design margins and/or sensitivies to wafer-fab process and parametric parameters.
3.



Execute design-of-experiments with process window corner lot to establish spec compliance of each product across full wafer-fab process window.
4. Execute qualification cycles for Si and package to automotive, industrial, and commercial standards (as per the primary product market)
5. During these various stages of Post-Silicon validation, you will interact with various cross-functional teams such as Design, DfT, Design Validation, Program Management, QRE/CQE, and Bench Characterization and Apps development teams
6. Will actively own or be part of a team that owns ATE Test Solutions, including HW design, socket design, ATE Resource Allocation, Board Schematic, Layout, and Diagnostic code
7. Will own product from bring-up to RTM (~12-14mo) and also own all the Product Entitlement goals and critical metrics for a successful ramp

- The candidate, in this role, is expected to lead and assist in defining and writing up test-specs for automation as well as STML (standard test methods library) to be used across multiple ATE tester platforms.
- Document gaps, lessons learned, and best practices with Design DFT teams to address on future products

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Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 ENGR II, PRODUCT; PROD&TEST (Karnataka)
🏢 ON Semiconductor
📍 Karnataka