- As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge High-Speed IO interfaces (PCIe, USB2/3, MIPI- UFS & PLL). You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of SERDES IP’s and perform failure analysis to root-cause a design problem.
- You will be working with system engineering and Hardware applications engineering teams across the globe in a time critical workplace.
- Required Experience: 3-6 Years of Post silicon Validation/Electrical Characterization.
- Good understanding of Characterization/SI methodology of High-Speed IO interfaces
- Experience in Instrument handling of JBERT, Oscilloscope, Network-Analyzer, Logic Analyzer, Signal Generators is must.
- Good command in PYTHON
- C/C++ Programming Knowledge is plus
Experience (years) : 3-6 years
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent