Ceremorphic AI hardware combines knowledge across many domains, including AI, compilers, computer architecture, analog circuits, and memories.
The candidate would own and drive the physical implementation of next-generation SOCs and assume the below responsibilities.
- Understand the requirements and define physical implementation methodologies.
- Collaborate with architecture, design, front end, and CAD teams to deliver high-quality physical designs.
- Implement and verify designs at all levels of hierarchy in the SOC.
- Interact with foundry over matters of technology, schedule, and signoff
- Supervise resource allocation and scheduling.
Key Requirements
- Hands-on expertise in all of the following areas: Floorplanning, Power planning, Logic and clock tree synthesis, Placement, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
- Full chip/ top-level expertise in multiple chip tape-outs.
- Positive understanding of SCAN, BIST, and ATPG.
- Strong background in TCL/Perl programming is a must.
- Expertise in double patterning process nodes is desirable.
- Expertise in Cadence RTL-to-GDSII flow is preferred.