Minimum qualifications Bachelor s degree in Electrical Engineering or a related field or equivalent practical experience 5 years of experience in SoC DFT aspects Experience with ATPG Low Power designs Memory BIST JTAG IJTAG tools and flow Experience with DFT EDA Tool Tessent Preferred qualifications Experience in working on SoC Level DFT Experience in Synthesis Lint LEC and DFT timing and STA Experience in a scripting language such as Perl Python Knowledge of high performance design DFT techniques Understanding of the end-to-end flows such as Design Verification DFT and PD Ability to scale DFT with a focus on area overhead About the job Be part of a team that pushes boundaries developing custom silicon solutions that power the future of Google s direct-to-consumer products You ll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences delivering unparalleled performance efficiency and integration In this role you will work on SOC Design for Test DFT Architecture to implement and validate from the SOC level You will work on SOC level ATPG and MBIST pattern generation to deliver and support post-silicon bring-up including subsystem level pattern retargeting The role requires working with the product engineering team on silicon bring-up and writing basic scripts to automate the DFT flow Additionally you will communicate and work with multi-disciplined and multi-site teams The Platforms and Devices team encompasses Google s various computing software platforms across environments desktop mobile applications as well as our first-party devices and services that combine the best of Google AI software and hardware Teams across this area research design and develop new technologies to make our user s interaction with computing faster and more seamless building innovative experiences for our users around the world Responsibilities Perform SOC level Memory Testing and repair feature verification ATPG pattern generation retarget and ensure coverage goals are met Develop and release the SOC DFT STA Constraint and validation along with RTL signoff checks Work on gate level simulation both no-timing and timing Integrate SOC DFT Scan architecture IJTAG network integration and verification Integrate and verify PHYs and Mixed-Signal IP DFT along with BSCAN Google is proud to be an equal prospect workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race color ancestry religion sex national origin sexual orientation age citizenship marital status disability gender identity or Veteran status We also consider qualified applicants regardless of criminal histories consistent with legal requirements See also Google s EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation please let us know by completing our Accommodations for Applicants form

📌 Senior Silicon Dft Engineer (Karnataka)
🏢 Important Business
📍 Karnataka