Job Requirements Formal Verification Engineer Overview We re looking for a highly skilled Formal Verification Engineer to join our team You ll be responsible for using formal methods to ensure the correctness and functional safety of our cutting-edge hardware designs This role requires a deep understanding of digital logic formal verification methodologies and a passion for solving complex challenging problems Responsibilities Develop and execute formal verification test plans for complex RTL designs Apply formal verification techniques including model checking theorem proving and equivalence checking to verify hardware designs Work closely with design and DFT Design for Test teams to understand design specifications and identify critical properties to verify Identify debug and resolve functional bugs and corner-case issues in RTL using formal methods Develop formal properties assertions using languages like SystemVerilog Assertions SVA and PSL Property Specification Language Create and maintain formal verification environments and flows Collaborate with design and architecture teams to improve design quality and reduce simulation cycles through early adoption of formal methods Document verification results and methodology to ensure design correctness and quality Qualifications Education Bachelor s or Master s degree in Electrical Engineering Computer Science or a related field Experience 4 years of experience in formal verification or ASIC FPGA design verification Technical Skills Proficiency with formal verification tools such as JasperGold VC Formal or FormalPro Solid knowledge of SystemVerilog Assertions SVA is a must Solid understanding of digital logic design computer architecture and RTL Register Transfer Level design languages like Verilog or SystemVerilog Experience with scripting languages e g Python Perl Tcl for test automation Familiarity with simulation-based verification methodologies e g UVM is a plus

📌 Formal Verification (Karnataka)
🏢 Quest Global
📍 Karnataka