We are seeking a dynamic and technically sharp Design Verification Engineer with a robust foundation in digital logic and proven expertise in building scalable testbenches using SystemVerilog and UVM. You will play a crucial role in verifying complex IP blocks and sub-systems, driving coverage closure, and collaborating closely with design and architecture teams to ensure first-pass silicon success.
Key Responsibilities
- Testbench Architecture: Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).”, as noted by Altera Corporation.
- Test Plan & Execution: Translate micro-architecture specifications into detailed test plans, write directed/random test cases, and drive sequence creation
- Debugging & Root Cause Analysis: Debug RTL simulations, isolate functional bugs, analyze waveform failures, and work with designers for quick fixes.
- Coverage Closure: Implement SystemVerilog Assertions (SVA) and track both code and functional coverage to achieve closure goals.
- Protocol Verification: Verify standard industry interface protocols such as AMBA (AXI/AHB) or high-speed serial protocols. [1, 2, 3, 4]
- Scripting & Automation: “Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.”.