Experience with SystemVerilog, UVM, and Cadence Xcelium/vManager is required;
Prior automotive SerDes DV experience is mandatory Block and chip-level functional verification of the ASA IP integration, ASA link data path, and all ASEP application streams.
- UVM testbench architecture for asa ip , asep application layer, and end-to-end CSI-2-to-ASA link scenarios • Constrained-random stimulus covering: PHY power-up sequences, TDD mode switching, light sleep, speed-grade change, IBG timing, double-sync header detect • ASA IP simulation model integration (gate-level and behavioural); PHY AMS/mixed-signal co-simulation • Protocol checkers for ASA-ML DLL containers, ASEP framing (stype, SOP/EOP, CRC), OAM transactions, and LLS security frames • Regression management; coverage closure (functional + code); formal CDC/reset verification (Cadence JasperGold) • Security scenario coverage: key exchange OAM flows, AES-GCM tag verification, authentication-only vs encryption modes