The Job Title: Senior RTL Verification Engineer - 5-10 Yrs
No. Of Positions: 6
Work Location: Bangalore
Key Responsibilities:
1. Build complex UVM/SystemVerilog testbench components and architectures.
2. Drive functional and code coverage closure to ensure design robustness.
3. Collaborate with design teams to debug complex architectural and micro-architectural issues.
4. Languages & Methodologies: Proficiency in SystemVerilog and UVM (Universal Verification Methodology).
5. Verification Expertise: Experience in testbench development, constrained-random verification, functional coverage, and code coverage.
6. Debugging: Strong waveform debugging skills and familiarity with industry-standard simulators (Synopsys, Cadence, or Mentor Graphics).
7. Domain Knowledge: Understanding of SoC/IP protocols (e.g., AMBA AXI/AHB/APB, PCIe, DDR, etc.) is a solid plus.