Senior Memory Layout Engineer

Location: Bengaluru, India

Experience: 4–8 Years

Role

Join our Memory Design team to develop high-performance SRAM, ROM, Register File, and Compiler-Based Memory layouts for advanced-node SoCs. You will drive memory layout implementation from device level to top-level integration, ensuring robust quality, manufacturability, and first-pass silicon success.

What You'll Do

Design and implement memory layouts including SRAM, ROM, Register Files, and memory compiler IPs.

Develop bitcell arrays, sense amplifiers, decoders, column muxes, row/column periphery, and top-level memory integration.

Perform floorplanning, device matching, routing, shielding, guard ring implementation, and layout optimization.

Drive DRC, LVS, ERC, Antenna, Density, DFM, EM/IR, and physical signoff closure.

Collaborate with Circuit Design, Physical Design, Reliability, and Process teams to achieve timing, area, and yield targets.

Support layout migration across technology nodes and process variants.

Contribute to methodology improvements and layout automation.

What You Bring

4–8 years of hands-on experience in Memory Layout.





Strong expertise in SRAM, ROM, Register Files, Memory Compilers, Bitcells, Sense Amplifiers, Decoders, and Periphery Layout.

Experience with Virtuoso XL/Studio, Calibre/PVS/ICV, StarRC/Quantus, and physical verification flows.

Solid understanding of advanced technology nodes (FinFET preferred) and layout techniques for matching, shielding, isolation, and reliability.

Knowledge of DRC/LVS/ERC, DFM, Antenna, EM/IR, and physical signoff methodologies.

Positive scripting skills (Tcl/Python) are an added advantage.

Preferred Qualifications

Experience with compiler-based memory architectures and top-level memory integration.

Exposure to advanced nodes (7nm/5nm/3nm) and low-power memory design.

Strong debugging, problem-solving, and collaboration skills.

We're Looking For

Engineers with deep memory layout expertise who are passionate about building high-density, high-performance memory IPs and delivering robust silicon through technical excellence and innovation.

📌 Senior Memory Layout Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru