Role Overview

Collaborate with architects and design engineers to understand IP specifications and define verification strategies and test plans.

Develop reusable constrained-random verification environments using SystemVerilog.

Create directed and random test cases to validate functionality and uncover bugs.

Build verification components such as drivers, monitors, scoreboards, and checkers.

Execute regressions, debug failures, and work closely with design teams for issue resolution.

Define and track functional/code coverage to ensure verification completeness.

Develop automation scripts using Python/Perl/Tcl to improve efficiency.

Participate in technical reviews and provide feedback on design and verification plans.

Preferred Profile

Bachelor’s/Master’s degree in Electronics and Communication.

5+ years of experience in FPGA design verification.

Strong expertise in Verilog/VHDL and SystemVerilog.

Experience with CDV (Coverage-Driven Verification) and ABV (Assertion-Based Verification).

Familiarity with protocols like PCIe, I3C, and Ethernet is a plus.

Solid scripting skills (Python, Perl, Tcl).

Excellent debugging, analytical, and communication skills.

📌 Senior FPGA Design Verification Engineer (Bengaluru)
🏢 prodigy technovations
📍 Bengaluru