FPGA Design Engineer –

Experience Range: 3 to 15+ Years

Location: Bangalore / Hyderabad / Noida / Ahmedabad/ Chennai/ Mumbai

Role Overview The FPGA Design Engineer is responsible for design, implementation, verification, and bring-up of FPGA-based systems used for functional validation, performance acceleration, prototyping, and product deployment. The role involves RTL design, timing closure, CDC handling, FPGA-specific optimizations, and collaboration with ASIC/SoC, verification, and system teams across domains such as datacenter, networking, automotive, AI accelerators, and debug platforms.

Core Responsibilities (All Levels)

Design and implement FPGA RTL using Verilog, VHDL, or SystemVerilog

Perform FPGA synthesis, place & route, and timing closure

Handle multi-clock and clock domain crossing (CDC) scenarios

Integrate standard protocols such as AXI, APB, I2C, SPI, and UART

Develop testbenches and perform FPGA-level simulation and debug

Support FPGA bring-up, board-level debug, and performance validation

Collaborate with ASIC/SoC teams for RTL correlation and emulation use cases

Automate FPGA flows using Tcl, Python, or Shell scripts

Senior FPGA Design Engineer – 3 to 5 Years

Develop block-level RTL targeted for FPGA platforms

Run basic synthesis, implementation, and timing analysis

Resolve straightforward timing, CDC, and functional issues

Support FPGA simulation and initial board bring-up





Assist in protocol integration and testbench development

Lead FPGA Design Engineer – 6 to 9 Years

Own end-to-end FPGA design for blocks or subsystems

Drive timing closure and FPGA resource optimization

Manage complex multi-clock designs and high-speed interfaces

Integrate FPGA designs for SoC emulation, validation, or prototyping

Work closely with RTL and DV teams to resolve functional issues

Support board-level debug and FPGA-to-silicon correlation

Member Technical Staff / Principal FPGA Design Engineer – 10+ Years

Define FPGA architecture and design strategy for platforms and products

Own complex FPGA-based subsystems such as debug controllers or accelerators

Lead performance scaling, timing closure, and reliability signoff

Drive FPGA-to-ASIC migration and correlation strategies

Establish reusable FPGA frameworks, automation, and best practices

Mentor FPGA engineers and provide technical leadership

Interface with customers, system architects, and EDA vendors

Tools & Skills

FPGA Tools: Xilinx Vivado, Vivado HLS, Intel Quartus

Languages: Verilog, VHDL, SystemVerilog

Protocols: AXI, APB, PCIe (as applicable), I2C, SPI, UART

Debug: Integrated Logic Analyzer (ILA), SignalTap

Platforms: Xilinx UltraScale / UltraScale+, RFSoC, Intel Agilex

Scripting: Tcl, Python, Shell

📌 Semiconductor Engineer (Bengaluru)
🏢 Tata Consultancy Services
📍 Bengaluru