- Execute daily simulations, debug test failures, and isolate root causes.
- Write robust test cases based on verification plans.
- Maintain regression suites and track bug reports.
Key Skills Required:
- Languages & Methodologies: Proficiency in SystemVerilog and UVM (Universal Verification Methodology).
- Verification Expertise: Experience in testbench development, constrained-random verification, functional coverage, and code coverage.
- Debugging: Strong waveform debugging skills and familiarity with industry-standard simulators (Synopsys, Cadence, or Mentor Graphics).
- Domain Knowledge: Understanding of SoC/IP protocols (e.g., AMBA AXI/AHB/APB, PCIe, DDR, etc.) is a robust plus.