N- Top-level (SOC) level basic industry standard Arch knowledge
N- SoC & IP level Integration knowledge
N- IPXACT knowledge
n- IORING and Phys & GPIOs basic functionality
N- Design Partitioning(Tilification) knowledge
N- Design RTL quality checks:
N
n
- Clock domain crossing(CDC)
N
- Reset domain crossing(RDC)
N
- LINT
n
- VSI
N
- UPF knowledge
n
- LEC(Logic equivalence check)
N
- Timing concepts & SDC knowledge
N
n- Tools knowledge:
N
n
- Vc_static or equivalent other tools(VSI)
N
- VC_spyglass LINT, CDC and RDC
N
- 0in
n
- Formality and conformal LEC tool
N
n- Design and scripting languages:
N
n
- Verilog and SV
N
- Perl
n
- Python
N
- TCL
n
📌 Rtl Design Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru
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