1. Understanding of low power design features and optimization techniques, including static and dynamic power saving schemes around architecture, design and power management.
2. Ability to balance trade-offs between power, performance, and area
3. Verilog or System Verilog experience and fundamental RTL design skills.
4. Experience using tools for power analysis, power delivery and signoff. (e.g. PrimePower, PowerArtist, PP-RTL)
5. Knowledge of ASIC Physical Design flow from RTL through Synthesis, Place & Route.
Valuable to have :
1. Background in running simulation and emulation tools [ VCS, Palladium, Zebu ]
2. Knowledge around graphics benchmarks/workload analysis.