Role SummaryWe are seeking a Senior Lead Digital Designer to lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, and multi‑gig automotive SerDes technologies).The role involves driving digital micro-architecture, state machines, PCS functionality, safety mechanisms, and end‑to‑end digital design across the PHY.Key Responsibilities1. Architecture & Technical LeadershipDefine and own digital subsystem micro‑architecture for Automotive Ethernet PHYs, including:PCS pipelines and encoding/decoding logicScramblers/descramblers, CRC engines, alignment & framingPacket processing, link monitoring, error handlingInterface logic (MII, RMII, RGMII, GMII, XGMII depending on product line)Processor based SoC designPerform system‑level partitioning between digital, analog/mixed-signal, and firmware components.Lead feasibility studies, power/performance trade-offs, and digital architecture exploration.2. RTL Design & ImplementationDevelop high-quality RTL (Verilog/SystemVerilog) for control, datapath, and protocol logic.Drive digital front-end flows including:Lint, CDC/RDC, reset architecture, synthesis guidanceTiming constraints and logic optimizationWork with DV to define coverage goals, corner cases, and feature verification plans.3. System‑Level OwnershipTranslate system requirements, IEEE 802.3 specifications,



and architecture documents into robust digital designs.Work with mixed-signal teams to define:Control interfaces to analog front‑end blocksCalibration engines, register programming flows, and digital‑analog interaction modelsContribute to bring‑up sequences, compliance testing, and system validation.4. Automotive Quality & Functional SafetyEnsure compliance with Automotive Ethernet standards, ISO 26262, and AEC‑Q100 expectations.Define and implement:Safety mechanisms (BIST, LBIST/MBIST, error detection schemes)Diagnostic monitors, timeout recovery logic, watchdogs, and fault reportingParticipate in FMEDA, DFA, and functional safety analysis.Required QualificationsMasters in Electrical Engineering, Computer Engineering, or related discipline.7+ years experience in digital design for PHY, SerDes, networking ASICs, or communication ICs.Strong expertise in:Verilog/SystemVerilog RTL designHigh‑speed digital logic, state machines, control logicIEEE 802.3 Ethernet PCS, link training, and system control flowsSynthesis, STA, CDC/RDC methodologyProven track record across multiple production tape-outs.Preferred QualificationsExperience with Automotive Ethernet standards: 10BASE‑T1S, 100BASE‑T1, 1000BASE‑T1, 10GBASE‑T1.Familiarity with PHY firmware-driven initialization and configuration flows.Robust debugging skills with logic analyzers, protocol analyzers, and post-silicon validation.Background in safety‑critical digital logic designs.

📌 Staff Digital Design Engineer (Bengaluru)
🏢 NXP
📍 Bengaluru