Should be very solid in Synthesis Timing concepts
Should understand .lib very well. Should be aware of all types of libs like NLDM, CCSM, ECSM etc.
Should have knowledge of DC-topo of similar concepts in other tools (RTL Compiler, talus
Timing basics should be very robust
Should understand the clocking structures and concepts very well.
Should have handled both block and top level. Should know the concepts of budgeting other techniques to handle hierarchical designs
Should have done both pre and post layout STA
Should have basic knowledge of Formal verification, Spyglas

Experience (years) : 7+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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📌 Sta Lead Karnataka (India)
🏢 Mirafra
📍 India