31 Jul
|
Mirafra
|
Karnataka
Should be able to handle LP-aware synthesis of SoC, tweak the flow to meet PPA targets
Should be able to debug and resolve RTL2N LEC, N2N, LP-LEC issues
Should be able to run CLP and resolve gate level CLP violations
Familiarity with Multi-voltage, multi-power domain based Low power implementation
Cadence: Genus, LEC, CLP
Makefile based flow
Tcl based automation
Experience (years) : 7+ years
Education Qualification:
Bachelors/Master degree in electrical/electronic engineering or similar
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📌 Sta Low Power Professional Karnataka
🏢 Mirafra
📍 Karnataka