Job Summary

We are seeking a highly motivated DFT Engineer with solid experience in Scan Insertion, ATPG, MBIST, LBIST, JTAG/Boundary Scan, and Pattern Validation for complex ASIC/SoC designs. The candidate will be responsible for DFT implementation, verification, pattern generation, debug, and sign-off activities at both block and full-chip levels.

Key Responsibilities
Execute and support various DFT activities including Scan Insertion, ATPG, MBIST, LBIST, and JTAG/Boundary Scan implementation.
Perform DFT architecture development, integration, verification, and validation at block and full-chip levels.
Generate, validate, and debug scan and ATPG patterns to achieve targeted fault coverage.
Validate patterns with and without timing and perform DFT-related debug and coverage analysis.
Conduct DFT mode timing analysis and sign-off to ensure design readiness for tape-out.
Verify scan chains, scan compression logic,



and test structures across the SoC.
Work closely with Design, Verification, Physical Design, and Product Engineering teams to resolve DFT issues and ensure successful silicon bring-up

Required Skills
Robust hands-on experience in DFT implementation and validation for ASIC/SoC designs.
Solid understanding of:
Scan Insertion and Scan Chain Verification
ATPG and Fault Coverage Analysis
MBIST and LBIST Insertion/Validation
JTAG / Boundary Scan (IEEE 1149.x)
Scan Compression Techniques (XOR, Adaptive Compression, MISR, OP-MISR, etc.)
Pattern Generation, Simulation, Validation, and Debug
DFT Timing Analysis and Sign-off
Experience with both block-level and full-chip DFT flows.
Robust debugging and problem-solving skills.

📌 Dft Design Engineer Karnataka
🏢 Kasmo.ai
📍 Karnataka