Lead design or verification activities for Tensilica CPU/DSP processor cores, multiprocessor subsystems, and associated peripherals.
Develop and implement RTL micro-architecture using Verilog, ensuring adherence to timing, area, and power constraints.
Design and execute verification strategies including test plan development, UVM-based verification, functional diagnostics, and coverage analysis.
Perform simulation, debugging, synthesis, and place-and-route analysis using EDA tools.
Develop and maintain SystemVerilog assertions (SVA), functional coverage models, and verification settings.
Analyze and debug design and verification failures across RTL, gate-level, and system-level simulations.
Collaborate closely with design, verification, and EDA teams to ensure end-to-end chip design quality and closure.
Develop assembly-level diagnostics and support embedded software validation for processor subsystems.
Contribute to micro-architecture definition, design reviews, and cross-functional technical discussions.
Mentor junior engineers and contribute to best practices in design and verification methodologies.

📌 Lead Design Engineer Noida (India)
🏢 Cadence
📍 India