Key Responsibilities
Design, implement, and maintain functional verification environments for complex SoC and digital systems.
Perform verification using Verilog and/or VHDL in simulation and emulation settings.
Develop testbenches, verification components, and reusable verification IP using SystemVerilog and UVM.
Execute constrained random verification, regression testing, and coverage-driven verification methodologies.
Debug functional and performance issues using Cadence and other EDA tools.
Analyze verification results and perform root-cause analysis for design failures.
Develop automation scripts to improve verification efficiency and reduce manual effort.
Collaborate with design, RTL, architecture, and validation teams to ensure design correctness.
Support SoC-level verification for complex subsystems and multi-IP integration.
Contribute to verification planning, test strategy development, and coverage closure.
📌 Sr Principal Product Validation Engineer Noida
🏢 Cadence
📍 Noida
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