Key Responsibilities
Support ASIC digital implementation activities across the complete RTL-to-GDSII design flow.
Work on physical design optimization, timing closure, and power-performance-area (PPA) improvements for designs at 16nm and below technology nodes.
Analyze, debug, and resolve customer-reported issues related to place and route, timing, and implementation flows.
Collaborate with R&D; teams to validate recent Innovus features, report findings, and drive product improvements.
Execute design benchmarks and develop implementation methodologies and optimized design flows.
Support digital implementation and signoff activities including floorplanning, placement, clock tree synthesis (CTS), routing, timing analysis, and physical verification.
Gather and analyze tool behavior, design results, and customer feedback to improve product quality and performance.
Work closely with release engineering teams to track, prioritize, and resolve software issues.
Provide technical guidance and recommendations to customers on implementation challenges and best practices.
Develop automation scripts to improve productivity and streamline design and validation processes.

📌 Product Engineer Ii Noida
🏢 Cadence
📍 Noida