At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field7-10 years of hands-on DV experience in semiconductor/ASIC/SoC companiesDeep expertise in SystemVerilog and UVM (Universal Verification Methodology)Strong understanding of digital design fundamentals - RTL, timing, clocking, resetsExperience with industry-standard simulators: Xcelium, VCS, QuestaProficiency in coverage-driven verification - functional, code, and toggle coverageHands-on experience with formal verification tools and flowsExperience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similarStrong debug skills - waveform analysis (Verisium, SimVision)Familiarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation Core Responsibilities Strategy and ArchitectureVerification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure. Testbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers. Feature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing. Execution and Technical LeadershipCustomer Interaction: Technically lead DV execution of small to mid-sized customer ASIC projects. Handle customer interactions. Convert high level customer requirements into DV execution plan. Development: Write complex test cases and sequences to achieve high functional coverage. Debug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes. Constraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.



Formal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss. Metric ManagementCoverage Analysis: Monitor and analyze functional and code coverage metrics. Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior. Sign-off: Define the "definition of done" and provide final technical approval for the verification phase. Soft Skills and LeadershipMentorship: Guiding junior engineers on coding standards and debugging techniques. Cross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams. Project Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines. We're doing work that matters. Help us solve what others can't. Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs) Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/equal-employment-opportunity-policy.pdf) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected]. Privacy Policy:



Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en_US/home/privacy/privacy-policy.html) . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/e-verify-participation-poster.pdf) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. ? Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse setting and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

📌 Principal Design Engineer (Bengaluru)
🏢 Cadence Design Systems
📍 Bengaluru