Key Responsibilities:
Understand design specifications and develop verification strategies and plans.
Develop UVM/System Verilog-based verification settings.
Create testcases, scoreboards, monitors, assertions, and coverage models.
Perform block-level, subsystem-level, and SoC-level verification.
Drive functional, code, assertion, and toggle coverage closure.
Execute regressions and analyze simulation results.
Debug RTL and verification environment issues in collaboration with design teams.
Participate in reviews and verification sign-off activities.
Required Skills:
Robust expertise in System Verilog and UVM.
Experience in functional verification of ASIC/FPGA designs.
Robust understanding of verification methodologies and coverage-driven verification.
Hands-on experience with assertions (SVA), regression management, and debugging tools.
Knowledge of digital design concepts and RTL architecture.