Key Skills: Static Timing Analysis, Asic, SOC, RTL Design, Physical Design, RTL, Asic Design, DFT, Implementation, DFT Design

Roles and Responsibilities:
Perform static timing analysis using Synopsys PrimeTime or Cadence Tempus and deliver timing signoff-ready results.
Develop, validate, and maintain SDC constraints including clocks, exceptions, false paths, and multicycle paths.
Analyze and debug setup/hold, transition, capacitance, and path-based violations; drive timing closure with PD teams via ECO support.
Execute MCMM analysis across PVT corners and modes and support cross-domain/interface timing analysis.
Lead STA reviews and documentation; resolve late-stage complex clocking and CDC-related signoff issues and mentor STA engineers.

Skills Required:
4 - 15 years of relevant experience in ASIC/SoC STA, timing constraints, and signoff.
Static Timing Analysis (STA)



fundamentals and hands-on experience for ASIC/SoC timing closure and signoff.
Solid RTL and RTL design understanding to identify missing constraints, unconstrained paths, and clock definition issues.
Physical Design awareness for timing ECO collaboration and analysis of setup/hold and transition violations.
ASIC/SoC timing signoff experience including constraint development and timing report generation for reviews.

Positive to Have:
DFT and DFT design experience for timing-aware integration and signoff readiness.
Implementation experience related to timing closure execution and ECO strategy support.

Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.

📌 Static Timing Analysis Sta Maharashtra
🏢 Careernet
📍 Maharashtra