System-on-Chip (SoC) Design Engineer Location: Bengaluru, India Experience: 5–12 Years Role: Design and implement high-performance SoC subsystems from microarchitecture to silicon.

Collaborate with architecture, verification, DFT, STA, and physical design teams to deliver high-quality, PPA-optimized RTL for next-generation AI, Compute, and Networking SoCs.

Responsibilities Develop microarchitecture and RTL using Verilog/System

Verilog.

Design datapaths, pipelines, FSMs, memory interfaces, and control logic.

Integrate SoC IPs and AMBA-based interconnects (AXI/AHB/APB).

Optimize designs for Power, Performance, and Area (PPA).

Drive RTL quality through Lint, CDC/RDC, synthesis, and debug.

Support timing closure, verification, and silicon bring-up.

Required Skills 5–12 years of ASIC/SoC RTL Design experience.

Robust microarchitecture and RTL design expertise.

Proficiency in Verilog/System

Verilog and ARM-based SoC architecture.

Experience with AMBA protocols, high-speed interfaces, and Synopsys Design Compiler.

Hands-on with Lint, CDC/RDC, VCS/Xcelium/Questa, and Python/Tcl/Perl scripting.

Exposure to advanced nodes (7nm/5nm/3nm) is a plus.

📌 System-on-Chip Design Engineer (India)
🏢 Leadsoc Technologies
📍 India