Category: Engineering, Hire Type: Employee, Remote Eligible: No

What You'll Be Doing

- Design, develop, and maintain Verification IP using SystemVerilog and UVM for industry-standard protocols including AMBA, PCIe, USB, Ethernet, UEC, UAL, and MIPI
- Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies
- Code sequences, test scenarios, and checkers that drive coverage-based verification across functional and code coverage dimensions
- Debug complex simulation failures across multi-layer protocol stacks, identifying root causes in both VIP logic and customer integration environments
- Enhance existing VIP products for performance, reusability, and scalability as protocols evolve and customer use cases expand
- Support customers during VIP integration and deployment, troubleshooting issues, answering technical questions, and ensuring successful bring-up
- Collaborate with Design IP teams, RD engineers, and field application teams to align VIP capabilities with product roadmaps and customer needs

The Impact You Will Have

- Your VIP will enable faster, more reliable verification for semiconductor companies building next-generation SoCs and AI-powered products
- Coverage-driven verification strategies you implement will catch critical protocol violations before they reach silicon, saving months of debug time downstream
- Enhancements you make to existing VIP products will improve performance and expand protocol support across the Synopsys IP portfolio
- Customer deployments you support will directly influence how engineers at leading semiconductor companies adopt and trust Synopsys VIP




- Verification plans you create will set the standard for how protocol compliance is validated across complex, multi-protocol designs
- Collaboration with Design IP teams will tighten the feedback loop between design and verification, improving quality across both disciplines
- Your work will contribute to a VIP product line used globally in semiconductor development, affecting how chips are verified at scale

What You'll Need

- Bachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience
- 5+ years of hands-on experience developing Verification IP
- Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments
- Specializing in NVMe protocols (mandatory) and PCIe (desirable) or deep working knowledge of at least two industry-standard protocols USB, Ethernet or MIPI
- The ideal candidate should have hands-on experience with BFM, IP, or VIP development and integration.
- The role requires a solid understanding of verification methodologies and protocol compliance. Strong problem-solving skills and the ability to work independently or as part of a team are important.
- Demonstrated ability to create and execute coverage-driven verification plans, including functional and code coverage analysis




- Experience debugging complex simulation failures and resolving issues across protocol layers and integration boundaries
- Experience working directly with customers or field teams during product deployment is a robust plus
- Excellent communication skills and a proactive approach to technical challenges are highly valued.

Who You Are

- You can read a protocol specification and translate it into a verification plan that covers not just the happy path but the corner cases that break real designs
- Debugging a failing sequence across thousands of lines of log output does not drain you, it engages you because you know the answer is in there somewhere
- You bring strong opinions about what good VIP architecture looks like, and you are willing to push back when a shortcut will create technical debt six months from now
- Working with customers during integration feels like a natural extension of your work, not a context switch, because you want to see your VIP succeed in the field
- You are organized enough to manage multiple VIP enhancements, customer issues, and verification plans in parallel without losing track of quality or deadlines
- When a task is 90% done, you are the person who finishes the last 10%, writes the documentation, and makes sure it actually works before calling it complete

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Locations: Noida, Uttar Pradesh, India

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 R&D Engineering, Staff Engineer (Uttar Pradesh)
🏢 Synopsys
📍 Uttar Pradesh