An expert level with developing UVM-based SV test-benches. Experienced with defining block, sub-system and SOC top level test plans. Relevant hands-on experience with PCIe and NVMe is a must. Deep understanding and knowledge of verification methodologies, flows and quality metrics. Great debugging and problem-solving skills. Team player with outstanding interpersonal communication skills. At least 5 years of relevant experience in NVMe/PCIe domain. Strong and relevant expertise with ASIC simulation tools and advanced verification methods. Expert level in verification languages such as UVM and System Verilog. Relevant experience with writing block-level and SoC test-plans. Education: B.S. in electrical engineering, computer science with extensive industry experience.