If you like connecting design intent with silicon reality, this role hits that sweet spot.

- 5–9 years in ASIC design and implementation
- Strong experience in Synthesis, STA, DFT, Lint, and CDC
- Hands-on with timing constraints and closure
- Experience with Tempus and PrimeTime tools
- Strong understanding of MMMC, SDF, and GLS support
- Experience in timing model generation and validation
- Ability to collaborate with design and SoC teams
- Solid analytical and debugging skills

If you enjoy solving timing puzzles others avoid, you’ll thrive here.

• Working knowledge of Synthesis, DFT, STA, Lint & CDC

• Work closely with design teams to understand the requirements and constraints of the design.

• Write and implement block level and top-level constraints for synthesis and STA.

• Experience of performing STA preferably with both Tempus and Primetime

• STA and Timing closure using MMMC in both functional and DFT modes

• Experience on SDF generation and validation and support to functional verification team during GLS.

• ETM /timing model generation and validation at IP level.

• Working in partnership with SoC teams to support the IP at SoC level.

📌 ASIC Engineer | ASIC Implementation Engineer (Synthesis/STA/DFT) (Bengaluru)
🏢 Important Group
📍 Bengaluru