Lead Digital Design Engineer

Location Bengaluru, India (Hybrid)

Position Summary

As a Lead Digital Design Engineer, you will be responsible for the design and implementation of complex digital IPs and SoC subsystems for next-generation AI infrastructure products. You will drive RTL development from architecture through implementation, collaborate closely with cross-functional teams, and provide technical leadership to ensure high-quality, first-pass silicon.

This role requires strong expertise in RTL design, SoC integration, and high-speed interfaces, along with the ability to mentor engineers and lead technical execution.

Key Responsibilities

- Lead the architecture, microarchitecture, RTL design, and implementation of complex digital IPs and SoC subsystems for high-performance connectivity products.
- Drive end-to-end ownership of design modules from specification through RTL development, integration, and silicon bring-up.
- Design high-quality, synthesizable RTL using Verilog/System Verilog, ensuring optimal performance, power, area (PPA), and scalability.
- Develop complex data paths, control logic, finite state machines, arbitration mechanisms, and protocol engines.
- Design and implement solutions for high-speed interfaces and protocols, including CXL, PCIe, Ethernet, and AXI-based interconnects.
- Collaborate with Architecture teams to define microarchitecture and review functional specifications.
- Partner closely with Design Verification teams to develop verification strategies, debug design issues, and achieve functional closure.
- Work with Physical Design teams to resolve timing, power, congestion, and implementation challenges through RTL optimization.
- Support synthesis, lint, CDC/RDC, STA, DFT, and design sign-off activities.
- Participate in design reviews and ensure compliance with RTL coding guidelines and design best practices.
- Drive debug and resolution of RTL,



integration, and post-silicon issues in collaboration with firmware, validation, and system engineering teams.

Required Qualifications

- Bachelors or Masters degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- 6-12 years of experience in digital design for complex semiconductor products.
- Robust expertise in Verilog/System Verilog RTL design.
- Experience with complete ASIC design cycles from microarchitecture through RTL implementation and silicon bring-up.
- Strong understanding of digital design fundamentals, computer architecture, and SoC integration.
- Experience with synthesis, lint, CDC/RDC, STA, and RTL sign-off methodologies.
- Excellent debugging and analytical skills.

Preferred Technical Skills

Experience in one or more of the following:

- Compute Express Link (CXL)
- PCI Express (PCIe)
- Ethernet MAC/PCS
- High-speed networking or connectivity IP
- AXI-based SoC architecture
- DMA engines
- Packet processing pipelines
- Memory controllers
- High-speed interconnects

Tools & Methodologies

- Verilog/System Verilog
- Synopsys Design Compiler
- Cadence Genus
- SpyGlass (Lint/CDC/RDC)
- Static Timing Analysis (STA)
- Git or other version control systems
- Python, Tcl, Perl, or Shell scripting

Preferred Experience

- Experience designing connectivity, networking, storage, or AI accelerator silicon.
- Proven track record of delivering successful ASIC or SoC tape-outs.
- Familiarity with high-speed protocols and data center technologies.
- Experience working in cross-functional global engineering teams.
- Exposure to low-power design methodologies and Design for Test (DFT) is a plus.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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