Description :

- Expertise in ASIC physical design

- Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR.

- Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization.

- Expertise in floor planning, methodology setup, and signoff processes for large IPs.

- Expertise in scripting (TCL, Python, Perl) for design flow automation.

- Drive SOC-level floor planning, partitioning, and die size estimation.

- Manage hierarchical design flows, including block-level pin placement and HFN

implementation.

- Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree).

- Provide technical mentorship to junior engineers and cross-functional teams.

- Own bump planning, including GPIO placement, pad ring generation, hard IP bump

integration, and RDL routing.

- Solid communication and problem-solving abilities

- Collaborate with RTL, STA, and verification teams for design closure.

- Utilize multiple EDA tools like Synopsys Fusion Compiler, ICC2, Design Compiler

📌 ASIC Physical Design Engineer (Chandigarh)
🏢 Vhunt4U
📍 Chandigarh