Company Description

MosChip® Technologies is a publicly traded Silicon and Product Engineering company with a global presence across Silicon Valley, USA, and India, employing over 2600 engineers. The organization delivers end-to-end silicon design, verification, systems, software, and device engineering solutions, including multimedia, mobility, connectivity, AI/ML solution design, and test automation. MosChip® also focuses on Digital IPs, Verification IPs, Mixed Signal IPs, and comprehensive Turnkey ASIC services.

The company has shipped millions of connectivity ICs and successfully completed more than 200 SoC tape-outs with a robust record of first-time-right silicon, offering engineers opportunities to work on complex and impactful semiconductor products. Role Description:

This is a full-time, on-site Senior Physical Design Engineer – PnR role based in the Greater Bengaluru Area. The role involves owning and executing block- and chip-level physical design activities, including floorplanning, placement, clock-tree synthesis, routing, and timing closure for advanced technology nodes. The engineer will collaborate closely with RTL, logic design,



and verification teams to ensure robust implementation, drive design-for-test and design-for-manufacturing requirements, and handle ECOs.

Day-to-day responsibilities include running and analyzing physical verification (DRC/LVS), power and IR-drop analysis, signal integrity checks, and optimizing performance, power, and area. The role also requires documentation of design methodologies, mentoring junior engineers, and contributing to continuous improvement of PnR flows and scripts. Qualifications:

Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification.

Well-versed with Physical Design verification signoff techniques such as Formal equivalence, IR&EM;, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc.

Positive understanding of Power, Performance and Area (PPA) optimization techniques.

Positive experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design.

Timing convergence (both tile-level and FCT), and full chip integration flows.

📌 Senior Physical Design Engineer Pnr Hyderabad
🏢 MosChip®
📍 Hyderabad