- Noida, Bangalore and Hyderabad

Role : Derive DFT architecture for a SOC in collaboration with product engineering team. Plan and track DFT implementation. Guide other DFT members in implementing DFT for hierarchical SOC. Support post silicon debug

Desired Skills

- 5+ tapeout as DFT lead/Sr DFT engineer.
- DFT architecture definition w.r.t. test time/cost, coverage, test power. Valuable experience/concept on all aspect of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
- DFT logic integration and verification.
- Experience on debugging low coverage.
- Gate Level DFT verification with and without timing.
- Pattern generation, verification and delivery to ATE team.
- Post silicon debug and support on failing patterns.
- Experience of leading small DFT team is plus.
- Good experience on EDA tools of reputed vendor like Mentor, Synopsis. LBIST experience is plus.
- DFT mode STA and timing closure support.

Experience : 6 to 9 Years

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📌 Technical Lead Engineer - DFT (India)
🏢 Keen Heads
📍 India