- 3 to 5 years of experience in PnR
- Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing
- Have hands-on experience in latest sub-micron technologies below 20nm
- Have done good number of Block level PnR with Timing Closure
- Familiar with Physical Verification flows (DRC/LVS/EM/IR)
- Experience in ECO implementation
- Familiarity with any of Scripting languages –PERL, TCL
- Should be a quick learner and have good attention to detail
- Must have positive communication & problem-solving skills.
Job Location: Bangalore/US
Designation: Senior Physical Design Engineer
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics