Sykatiya Technologies, believes in Technical Ability along with the Attitude of our highly talented team and reflects the same in the contributions to the customers’ project. Team comprises highly talented engineers and experts from Design Verification, DFT/Test, Physical Design and Analog Design for ASICs.
RTL/ IP Design
Experience: 3-12 Years
Location: Bangalore
- You have 5+ years of experience of digital ASIC front-end design
- Have a positive understanding of the design flow like RTL (VHDL, Verilog and/or SystemVerilog)
- Have experience of simulation tools like Questa or Xcelium and logic synthesis (e.g. Synopsys DC).
- You have experience of embedded microcontrollers and AMBA bus systems.
- You have a science/engineering Bachelor's degree and you speak English fluently.
📌 RTL/ IP Design (India)
🏢 Sykatiya Technologies
📍 India
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