Location: Location: Bengaluru/Bhubaneswar/Ranchi

Experience: 5 - 10 Years

Technical Requirements:

- Physical Design Implementation: Experience in block and SoC level PD

implementation, covering the entire flow from netlist to GDSII, including PnR/APR.

- Low Power Design: Proficient in low power design techniques.

- Flow Expertise: Hands-on experience with floorplanning, power planning,

placement, CTS (Clock Tree Synthesis), routing, extraction, and DFM (Design for

Manufacturing).

- Analysis Skills: Solid ability to perform congestion and timing analysis, with a

focus on achieving better QoR (Quality of Results).

- Sign-Off Expertise: In-depth knowledge of sign-off processes including STA (Static

Timing Analysis), DRC/LVS/Antenna/ERC checks, power analysis, IR/EM analysis,

LEC (Logic Equivalence Checking), and ECO (Engineering Change Order) for both

timing and functionality.

- Process Knowledge: Comprehensive understanding of the entire physical design

process from RTL to GDSII, encompassing floorplanning, placement,



CTS, routing,

and sign-off stages.

- ECO Implementation: Experience in implementing ECOs.

- PnR Tools: Hands-on experience with PnR tools such as Synopsys ICC II and

Cadence Innovus.

- Scripting Skills: Proficient in scripting languages like Perl and TCL, with experience

using various EDA tools.

Expectations from the Role:

- Debugging & Problem-Solving: Excellent debugging and problem-solving skills,

with the ability to tackle complex design issues.

- Communication: Effective communication skills for interacting with all

stakeholders.

- Focus & Commitment: Must be highly focused and committed to achieving project

goals and closing out tasks.

- Independence: Ability to work independently and manage tasks with minimal

supervision.

- Leadership: Possesses strong leadership skills with a proactive, go-getter attitude.

📌 Physical Design Engineer/Lead (India)
🏢 ARF DESIGN
📍 India