Sholinganallur, Tamil Nadu
Job Summary

Signal & power Integrity experience is mandatory

6-8 yrs of Strong experience in Signal Integrity and Power Integrity fundamental concepts.

Deep Understanding of S-parameter & its modelling concepts for Single ended and differential interfaces.

Experience in simulating (FD/TD) memory interfaces for Board and Package is required (DDR4/LPDDR4)

Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package is required (PCIe Gen3/4, SATA Gen3, USB3/3.1 and Display Interfaces etc.)

Good knowledge of Power Delivery Network, impedance profile analysis, IR Drop Analysis, and time domain Analysis.

Experience in extracting the PDN model of package and PCB power rails and perform decoupling capacitor optimization, Loop inductance analysis.

Robust knowledge in simulation tools specifically Hspice, Sigrity (2.5D and 3D-EM Must), ADS and other tools like Ansys SIwave, HFSS 3D. Cadence- PowerSI & PowerDC

Key Responsibilities
1.



To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations, contributing to the creation of seamless user experiences.
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.

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📌 Senior Design Lead (India)
🏢 HCLTech
📍 India