FPGA Design Engineer – Wireless Communications and HDL Coding

Responsibilities

- Design and implement wireless communication protocols on FPGA, including signal processing, modem architectures, channel coding, synchronization, filtering, and complete Layer 1 implementation.
- Develop complete wireless transmit and receive chains, integrating RF blocks with required interfaces and APIs.
- Use MATLAB/Simulink for algorithm modelling, simulation, validation, VHDL code generation, and FPGA implementation.
- Perform functional verification, timing closure, hardware debugging, system integration, hardware bring-up, board-level testing, and design validation.

Requirements

- 3+ years of hands-on FPGA design, development, and verification experience in the wireless domain.
- Bachelor's or Master's degree in Electronics and Communication.
- Solid knowledge of DSP, communication systems,



and wireless technologies.
- Proficiency in VHDL/Verilog/SystemVerilog and FPGA development tools.
- Experience implementing wireless communication protocols and complete transmit/receive chains on FPGA.
- Hands-on experience with MATLAB/Simulink and AMD Xilinx or Intel Altera FPGA platforms.
- Familiarity with FPGA verification, validation methodologies, and simulation tools.
- Candidates with proven wireless communication FPGA design experience will be preferred. Compensation will be commensurate with relevant design expertise and project experience.

Pay: ₹400,000.00 - ₹700,000.00 per year

Benefits:

- Life insurance
- Paid time off

Work Location: In person

📌 FPGA Design Engineer (India)
🏢 Paras Defence & Space Technologies
📍 India