Roles & Responsibilities

- Minimum 3 years of experience in areas of SOC-DFT Implementation and Integration
- Hands-on experience and knowledge of ATPG, ATPG-DRC clean-up, Pattern
- Generation, fault models, coverage analysis and improvement
- Hands-on experience with pattern generation for various fault models, Stuck-At, TDF, PDF, IDDQ
- Experience with pattern verification, simulation debug, ATE pattern delivery and silicon bring-up
- Experience with one or more scan/ATPG solutions with Tessent Scan, FastScan, TestKompress
- Synopsys DC, DFTC, DFTMAX, Tetramax
- Experience with pattern verification and debug VCS, Simvision, NC-verilog, Questa
- Desired experience with failure diagnostics, silicon debug and interfacing with ATE and test engineers for bring-up
- Preferred but not required MBIST implementation and experience with MBIST pattern generation and verification
- Preferred but not required experience with one or more MBIST solutions Tessent
- BIST,



MBIST Architect, SMS
- Experience with shell scripting, Verilog, Tcl and/or Perl/Python
- Strongly desired understanding of IEEE 1149.1, P1500 and Core-Based Testing Standards
- Desired experience with coverage improvement and yield improvement
- Desired experience with test constraint generation and working with STA for test mode timing closures
- Desired familiarity with DFX concepts
- With Excellent communication and interpersonal skills
- Very positive team player, self-motivated and creative in problem solving

Designation: Senior DFT Engineer

Experience: 4+ years

Location: Bangalore/Hyderabad/US

Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics

Number of Positions: 5

📌 Senior DFT Engineer (India)
🏢 pozibility technologies
📍 India