B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 1 tape out. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage

Experience Required: 5-10 yrs

Skills Required

- Top level die size estimation, floor planning, power estimation , power planning .
- IO Planning and package compatibility sign off.
- Netlist and constraint sign in checks and validation.
- Prime time constraint development at full chip level and clean up.
- Design implementation environment setup.
- Static and Agile power analysis at the top level.
- Netlist to GDS II implementation at chip level.
- Hierarchical chip planning, block planning , block level constraint development, hierarchical clock tree implementation, block integration and chip finishing.
- Multimode multi corner optimization and closure at top level.




- Clock tree synthesis and advanced clock tree implementation at full chip level.
- Handling of PLL, TXR, DDR and other analog components during implementation.
- IO ring customization for multi IO designs.
- Full chips upward of 1M Instances to 20M+ instances.
- Top level timing closure with sign off STA in MMMC with Xtalk and OCV.
- Top level ECO implementation strategy development for netlist ,RTL and timing level changes
- Scripting experience in Perl/TCL.
- Flow customization and fine tuning for Power , Performance, Area.
- Exposure to DFM and DFM compatible implementation.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions .
- Exposure to designs critical for power, area and timing at the same time.
- Technologies from 28nm and below.
- Exposure to Physical design project planning and execution.
- Technical leadership and ability to mentor and make the team deliver.
- Location: Bangalore

- send your resumes to [email protected]

Location: Bangalore, Hyderabad, Chennai and Delhi

send your resumes to [email protected]

📌 Sr Lead Physical Design (India)
🏢 The Nanopore Site
📍 India