Bangalore, Karnataka
Job Summary
IC Package Design Engineer with 8+ years experienced

Experience with Cadence Advanced Package designer, IC Package Design experience with Cadence APD Layout tool
Good understanding of package/substrate design and package assembly rules related to flip chip designs.
Good knowledge and experience in BGA ball map assignment and Die bump analysis for routability.
Already done 4 to 5 tape outs.

Exposure to different package technologies such as MCM, flip chip / wire bond, 3D, 2.5D etc., added advantage
Expertise in High-Speed Complex Package and PCB designs with HDI, Blind and Buried Via technologies.
Experience with PDN, SI/PI requirements of package layout.

Hands-on expertise with Package designs involving High Speed Parallel Bus interfaces including DDR, LPDDR, GDDR and HSIO interfaces including PCIe, SERDES.
Positive Exposure to Stackup design, DFM, DFA rules and adherence.
Should have expertise in constraint setting in APD layout tool.

Key Responsibilities
1.



To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations, contributing to the creation of seamless user experiences.
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.

Skill Requirements

IC Package Design, Flip Chip, FcBGA, MLO design, MLC design, 2.5D, 3D design experience, Cadence APD

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📌 Senior Design Lead (India)
🏢 HCLTech
📍 India