Job Summary

We are seeking an experienced Design Verification Engineer with expertise in Design for Debug (DFD) verification for complex ASIC/SoC designs. The ideal candidate should have strong hands-on experience in SystemVerilog, UVM, and system-level verification of Design for Debug features, along with knowledge of Intel VISA Mux architecture and AXI protocol.You will work closely with Design, Architecture, DFD, and Validation teams to develop robust verification environments, validate debug infrastructure, and ensure high-quality silicon.

Key Responsibilities

- Develop and execute system-level verification for Design for Debug (DFD) features.
- Build reusable UVM-based verification environments, testbenches, and verification components.
- Develop directed and constrained-random test cases using SystemVerilog and UVM.
- Verify debug infrastructure, visibility paths, and functional correctness of DFD implementations.
- Validate Intel VISA Mux architecture and associated debug features.
- Verify AXI-based interfaces and ensure protocol compliance.· Debug RTL, testbench, and simulation failures to identify root causes.
- Execute regression suites and analyze functional coverage to achieve verification closure.
- Collaborate with Design, Architecture, DFT/DFD, and Physical Design teams to resolve issues.




- Contribute to verification planning, coverage analysis, and methodology improvements.

Required Skills

- 7–10 years of experience in ASIC/SoC Design Verification.
- Solid hands-on experience in Design for Debug (DFD) Verification.
- Excellent programming skills in SystemVerilog (SV).
- Strong expertise in UVM (Universal Verification Methodology).
- Experience in system-level verification of Design for Debug features.
- Knowledge of Intel VISA Mux architecture or similar on-chip debug architectures.
- Strong understanding of AXI protocol and AXI-based verification.
- Experience in RTL debugging, constrained-random verification, assertions, and functional coverage.
- Good understanding of ASIC/SoC verification methodologies.

Preferred Skills

- Experience with Synopsys or Cadence simulation and debug tools (VCS, Xcelium, Verdi, etc.).
- Experience with scripting using Python, Perl, or Shell.
- Exposure to silicon debug, post-silicon validation, or hardware debug infrastructure.
- Strong analytical and debugging skills.
- Excellent communication and collaboration abilities.
- Experience leading verification activities or mentoring junior engineers.

Pay: ₹1,700,000.00 - ₹2,500,000.00 per year

Work Location: In person

📌 DFD Design Verification Engineer (India)
🏢 Spatial Alphabet
📍 India