ASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore (Bengaluru)

ASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore (Bengaluru)

02 Aug
|
Cisco Systems
|
Bengaluru

02 Aug

Cisco Systems

Bengaluru

Meet the Team
At Cisco Systems, the Client Optics Group (COG) Engineering team is at the forefront of building next-generation optical interconnect solutions powering high-speed networking. The team focuses on delivering cutting-edge 100G, 200G, and 400G per lambda technologies that enable scalable, high-performance data movement across modern infrastructure.
As a Layout Lead, you will work within a highly collaborative, cross-functional setting alongside analog and mixed-signal designers, digital engineers, packaging experts, process technologists, and validation teams. Together, you will drive end-to-end development of complex silicon solutions that are critical to Cisco’s innovation in optics and high-speed connectivity.

Your Impact
In this role, you will provide technical leadership and drive the physical implementation of high-performance analog and mixed-signal designs from concept through tapeout.
You will:
- Lead end-to-end layout development for complex analog, mixed-signal, and high-speed circuits including SerDes and PAM4 interfaces




- Own block-level and top-level floorplanning, placement, routing, and integration
- Translate circuit schematics and performance requirements into optimized, manufacturable layouts
- Optimize designs for parasitics, matching, signal integrity, power integrity, thermal behavior, and yield
- Ensure compliance with all physical verification requirements (DRC, LVS, ERC, EM/IR, density, reliability)
- Drive integration across analog, digital, and high-speed domains including clocking and control logic
- Support post-layout extraction, simulation closure, and tapeout readiness
- Partner with packaging teams on bump planning, pad ring, ESD, and overall package integration
- Identify and resolve layout challenges impacting performance, yield, or manufacturability
- Lead design reviews, assess trade-offs, and mitigate tapeout risks
- Improve layout methodologies, flows, and automation in collaboration with CAD teams
- Mentor juni

📌 ASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore (Bengaluru)
🏢 Cisco Systems
📍 Bengaluru

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