Frontend CAD DV Engineer (India)

Frontend CAD DV Engineer (India)

02 Aug
|
This opportunity
|
India

02 Aug

This opportunity

India

About this opportunity:

Are you a hands-on engineer and ready to shape the future of silicon verification methodology and tools on a global scale?

Join our Design Verification Methodology team — a newly established global group defining methodologies and EDA workflows across our R&D; sites in Bangalore, Austin, Stockholm, and Lund.

We are part of the Ericsson Silicon engineering unit, developing state-of-the-art ASICs and FPGAs at advanced technology nodes for Ericsson’s 5G and 6G product portfolio. Our environment offers deep technical challenges, opportunities for growth, and a wealth of expertise to learn from. Last year we started a recent Silicon R&D; center in Bangalore, ready to join?

What you will do:
- In this high-visibility role, you will shape the next generation of Front-End CAD (FECAD) methodologies, DV flows, and infrastructure for ASIC IP and SoC development.
- Major part of your work is to work with DV activities of our proprietary tools development.
- Your impact will be central in optimizing methodologies and EDA workflows,



driving efficiency and innovation across our global silicon engineering community.
- We are particularly interested in individuals with exposure to or interest in applying AI/ML techniques to silicon design and verification — a significant plus as we invest in AI-driven design automation.
- If you thrive on solving technical challenges, spotting opportunities for improvement, and driving continuous innovation, we’d love to have you on our team.

You will bring:
- Deep expertise in Testbench Architecture using SystemVerilog and UVM at IP, ASIC, and/or SoC level.
- Previous hands-on experience in scripting (Python, Perl, bash, csh, etc.).
- Strong knowledge of layered UVM environments, reusable testbench components, and block/subsystem/SoC-level verification strategies.
- Solid understanding of directed and constrained-random verification, SVA, functional and code coverage closure.
- Proficiency with front-end EDA tools: Verilog s

📌 Frontend CAD DV Engineer (India)
🏢 This opportunity
📍 India

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