Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
3-15 years of experience in Design for Testability (DFT) or a related field (experience with ASIC/SoC design a plus)
Basic understanding of digital design principles (combinational logic, sequential logic)
Working knowledge of DFT concepts (scan insertion, ATPG, fault coverage)
Familiarity with DFT tools and methodologies is a plus
Ability to learn quickly and adapt to new technologies
Strong analytical and problem-solving skills
Excellent communication and collaboration skills to work effectively in a team setting
Location: DFT - Bangalore, Noida, Kochi and if candidate is a lead then any location is fine
📌 Design for Testability Engineer (Bengaluru)
🏢 HCLTech
📍 Bengaluru
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