Memory Layout design Engineers (India)

Memory Layout design Engineers (India)

02 Aug
|
Zia Semiconductor
|
India

02 Aug

Zia Semiconductor

India

Experience : 2-5 Years Experience

- Understanding of memory compiler floor plan
- Memory Leafcell layout development
- Memory backend Qualifications (DRC/LVS/ERC/DFM)
- Electrical qualifications (EM/IR)

Interested candidates can send their resumes at : [email protected]

📌 Memory Layout design Engineers (India)
🏢 Zia Semiconductor
📍 India

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