STA Lead (Static Timing Analysis) – 10+ Years

Full-time

Experience : 10+ Years

Location : Bengaluru / Hyderabad / Noida

Job Summary

We are looking for an experienced STA Lead with 10+ years of expertise in Static Timing Analysis to lead end-to-end timing closure and signoff activities for complex SoCs on advanced technology nodes. The ideal candidate should be capable of independently driving timing signoff, leading customer interactions, mentoring engineering teams, and ensuring successful tapeouts.

Key Responsibilities

- Own and drive end-to-end STA flow from synthesis handoff to timing signoff.
- Perform timing analysis, timing closure, and signoff for high-performance SoCs.
- Analyze and resolve setup, hold, recovery, removal, SI, noise, and OCV timing violations.
- Perform timing signoff across multiple PVT corners and operating modes.
- Collaborate closely with Physical Design, RTL Design, DFT, CTS, and ECO teams to achieve timing closure.
- Drive ECO implementation and validate timing fixes.
- Perform constraint development, validation, and timing exception analysis.
- Generate and review timing reports, signoff documentation, and customer deliverables.
- Lead technical discussions and provide regular project updates to customers.
- Mentor junior STA engineers and provide technical guidance.
- Ensure successful project execution and tapeout delivery on schedule.

Required Skills

- 10+ years of hands-on experience in Static Timing Analysis (STA).
- Strong expertise in PrimeTime and/or Cadence Tempus.




- Excellent understanding of:
- Timing Constraints (SDC)
- MCMM Analysis
- OCV / AOCV / POCV
- SI (Signal Integrity)
- Crosstalk Analysis
- Clock Tree Analysis
- Timing ECO Flow
- Experience in advanced technology nodes (7nm / 5nm / 3nm / 2nm) is highly preferred.
- Robust knowledge of timing signoff methodologies and best practices.
- Excellent debugging and problem-solving skills.
- Strong scripting skills in TCL, Shell, or Python.
- Excellent communication and customer-facing experience.

Preferred Qualifications

- Successful tapeout experience on advanced technology nodes.
- Experience leading technical teams and mentoring engineers.
- Ability to independently own project execution with minimal supervision.
- Exposure to low-power designs (UPF/CPF) is an added advantage.

Education

- Bachelor's or Master's Degree in Electronics, Electrical Engineering, VLSI, or a related field.

Why Join Us?

- Opportunity to work on cutting-edge semiconductor designs.
- Exposure to advanced technology nodes and leading semiconductor customers.
- Collaborative engineering culture with opportunities for technical growth and leadership.
- Competitive compensation and career advancement opportunities.

Notice Period: Immediate to 30 Days Preferred

Pay: From ₹2,500,000.00 per year

Benefits:

- Leave encashment
- Provident Fund

Experience:

- STA: 10 years (Preferred)

Location:

- Bangalore City, Bengaluru, Karnataka (Required)

Work Location: In person

📌 STA Lead (India)
🏢 Astrasilica Technologies Private
📍 India