- Define micro architecture from datasheet or requirements document
- Perform RTL-level design, Synthesis, STA, CDC and Lint for any digital logic
- Perform module-level verification and lint checking
- Interact with verification engineers for test plan review, coverage debug
Required Skills
- B.Tech/M.Tech in Electronics/VLSI Engineering with experience of 3-5 years in ASIC Design
- Strong hands-on experience with Verilog RTL-level design, Synthesis, STA, CDC and Lint
- Should be able to work independently once the design requirements are specified
- Knowledge of standard interfaces viz., AXI, AHB, SAS, DDR, PCIe, Flash-Memory, OTN, I2C/SPI is a plus
- Knowledge of Perl, and EDA tools for LEC, Synthesis is a plus
- Must have valuable spoken and written communication skills
- Collaborate well in a team
- Lead will manage a team of engineers to perform the above tasks.
Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru
Ahmedabad
Bhubaneswar
Noida
Hyderabad
Pune
Onsite in India
San Jose, USA