Job Function Functional Formal Verification Engineer - Lead We are seeking an experienced Functional Formal Verification Engineer to join our team and lead formal verification efforts for complex digital designs As a Lead Formal Verification Engineer you will play a critical role in ensuring the quality and reliability of our digital designs Qualifications o Bachelor s or Master s degree in Electrical Electronics Engineering Computer Engineering or a related field o 5 years of experience in formal verification of complex IP SubSystem SoCs with a robust understanding of digital logic design and verification techniques o Expertise in formal verification tools and property specification languages e g SVA PSL as well as proficiency in HDLs such as System Verilog Verilog or VHDL o Experience with industry-standard EDA formal tools o Experience with scripting languages e g Python Tcl Perl and programming languages such as C C SystemC o Excellent problem-solving and analytical skills with the ability to debug complex issues and optimize verification performance o Strong communication and interpersonal abilities with experience working in a team environment and collaborating with cross-functional teams o Proven track record in technical leadership and mentoring with experience guiding junior engineers and contributing to the development of formal verification methodologies Responsibilities o Lead complete formal verification for single or multiple design blocks and IPs including developing and implementing formal verification strategies and test plans o Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality o Prove design properties identify bugs and collaborate with design teams to improve micro-architectures and ensure design correctness o Craft innovative solutions for verifying complex design architectures including developing re-usable and optimized formal models and verification code bases o Mentor junior team members and provide technical leadership in formal verification methodologies including training and guidance on industry-standard tools and techniques o Collaborate with cross-functional teams including design and verification to ensure seamless integration of formal verification into the overall verification flow Preferred Skills o Experience with CPU GPU or other complex digital architectures including knowledge of industry-standard protocols e g AXI CHI PCIe o Familiarity with UVM methodology and or other simulation-based verification methodologies o Experience with advanced FV performance optimization techniques such as abstraction methods property decomposition and other state-space reduction techniques o Expertise in Jasper or VC Formal products is highly desirable Job Locations o India Bangalore Job Function Functional Formal Verification Engineer - Lead We are seeking an experienced Functional Formal Verification Engineer to join our team and lead formal verification efforts for complex digital designs As a Lead Formal Verification Engineer you will play a critical role in ensuring the quality and reliability of our digital designs Qualifications o Bachelor s or Master s degree in Electrical Electronics Engineering Computer Engineering or a related field o 5 years of experience in formal verification of complex IP SubSystem SoCs with a strong understanding of digital logic design and verification techniques o Expertise in formal verification tools and property specification languages e g SVA PSL as well as proficiency in HDLs such as System Verilog Verilog or VHDL o Experience with industry-standard EDA formal tools o Experience with scripting languages e g Python Tcl Perl and programming languages such as C C SystemC o Excellent problem-solving and analytical skills with the ability to debug complex issues and optimize verification performance o Strong communication and interpersonal abilities with experience working in a team environment and collaborating with cross-functional teams o Proven track record in technical leadership and mentoring with experience guiding junior engineers and contributing to the development of formal verification methodologies Responsibilities o Lead complete formal verification for single or multiple design blocks and IPs including developing and implementing formal verification strategies and test plans o Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality o Prove design properties identify bugs and collaborate with design teams to improve micro-architectures and ensure design correctness o Craft innovative solutions for verifying complex design architectures including developing re-usable and optimized formal models and verification code bases o Mentor junior team members and provide technical leadership in formal verification methodologies including training and guidance on industry-standard tools and techniques o Collaborate with cross-functional teams including design and verification to ensure seamless integration of formal verification into the overall verification flow Preferred Skills o Experience with CPU GPU or other complex digital architectures including knowledge of industry-standard protocols e g AXI CHI PCIe o Familiarity with UVM methodology and or other simulation-based verification methodologies o Experience with advanced FV performance optimization techniques such as abstraction methods property decomposition and other state-space reduction techniques o Expertise in Jasper or VC Formal products is highly desirable Job Locations o India Bangalore

📌 Functional Formal Verification (India)
🏢 AMD
📍 India